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Altera_Forum's avatar
Altera_Forum
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11 years ago

Problem with SDRAM: works fine on Cyclone II but not on Cyclone IV

Hi forum,

This problem is getting me crazy! I have two boards, both with an Alliance AS4C8M16S-6TIN SDRAM, one has a EP2C5T144C8N and the other a EP4C15E22C7N. I'm using Qsys SDRAM controller to control the memory and a JTAG Avalon Master with system console to execute write and read commands, but it isn't working on the Cyclone IV board; when i read the memory, it looks like the timmings are off, even though they are the same as the Cyclone II, wich is working. Here's what i'm getting:

--- Quote Start ---

WRITE:

0x11111110 0x11111101 0x11111011 0x11110111 0x11101111 0x11011111 0x10111111 0x01111111

READ:

0x000a000a 0x11111111 0x11111111 0x11111111 0x24002400 0x11011101 0x01110111 0x01110111

--- Quote End ---

There are no timming violations in neither project, the only difference regarding timmings is the input clock, which is 48MHz on Cyclone II and 50 MHz on Cyclone IV, in both cases i'm using a pll to output a 96MHz clock. I've tested 3 different SDRAM chips, all three outputted the same bytes. I have no ideas left :(

Thanks for any help.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Post the PLL settings. For simple SDRAM (not the DDR), you have to use two clock outputs from the PLL. You will also have to use ODDR component for correct timing analysis.

    Please provide the link to the memory datasheet in order to check the access time of the memory. I can't remember correctly, but you have to supply one PLL output clock to the internal system itself and another output, with phase difference equal to access time of the memory, to the ODDR block, which is then goes to the output pin and finally the memory chip.

    E.g.:

    OUTCLK0 -> 96MHz, phase: 0ns

    OUTCLK1 -> 96MHz, phase: -5.4ns

    Please note, that I am using nanoseconds instead of degrees for phase difference as the degrees value would change if you would change the output frequency.

    You can first do the tests without the ODDR primitive, which should work, however you'll need it later. I would also recommend to start testing using lower frequency like 50MHz and go up when it's stable.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Here's the datasheet:

    http://www.alliancememory.com/pdf/dram/128m-as4c8m16s.pdf

    My PLL has 2 clocks, both 96MHz but one has a -3.0ns phase shift, which works on Cyclone II. I'll do some testing with -5.4ns phase shift and lower frequencies.

    EDIT: I got it working on Cyclone IV by compiling the Cyclone II project and changing the device and pin locations, any clue if there is a setting that i'm missing?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Well, i guess working 12 hours straight can mess up your sight, the phase shift i was using was -3.0 ps instead of ns...

    Thanks for your help Socrates, made me double check the PLL settings and find the error :P