Problem with SDRAM: works fine on Cyclone II but not on Cyclone IV

Post the PLL settings. For simple SDRAM (not the DDR), you have to use two clock outputs from the PLL. You will also have to use ODDR component for correct timing analysis.

Please provide the link to the memory datasheet in order to check the access time of the memory. I can't remember correctly, but you have to supply one PLL output clock to the internal system itself and another output, with phase difference equal to access time of the memory, to the ODDR block, which is then goes to the output pin and finally the memory chip.

E.g.:

OUTCLK0 -> 96MHz, phase: 0ns

OUTCLK1 -> 96MHz, phase: -5.4ns

Please note, that I am using nanoseconds instead of degrees for phase difference as the degrees value would change if you would change the output frequency.

You can first do the tests without the ODDR primitive, which should work, however you'll need it later. I would also recommend to start testing using lower frequency like 50MHz and go up when it's stable.