Problem with SDRAM: works fine on Cyclone II but not on Cyclone IV

Here's the datasheet:

http://www.alliancememory.com/pdf/dram/128m-as4c8m16s.pdf

My PLL has 2 clocks, both 96MHz but one has a -3.0ns phase shift, which works on Cyclone II. I'll do some testing with -5.4ns phase shift and lower frequencies.

EDIT: I got it working on Cyclone IV by compiling the Cyclone II project and changing the device and pin locations, any clue if there is a setting that i'm missing?