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Altera_Forum's avatar
Altera_Forum
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18 years ago

problem with resource sharing.......

i've a piece of hardware which does something like this:

a<= b xor c;

d<= e xor b xor c;

f<= g xor e xor b xor c;

i do all these operations in 1 clk cycle.......

but synthesizer does something like this.......

a <= b xor c;

d <= e xor a;

f <= g xor d;

this works fine in functional , post- tran and post -map... however in post par i get errors due to feedback......

can i somehow ask the synthesizer to not to share resource?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    --- Quote Start ---

    i do all these operations in 1 clk cycle

    --- Quote End ---

    I seems, that you're doing the operations in no clock cycle, respectively in combinational logic. If so, the optimizations that you name resource sharing actually don't affect the logical behaviour.

    If the assignment would be performed in clocked process, the a result register is one clock behind the input term and could not replace it in another expression.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Sumanthhv,

    There is no ressource sharing. The compiler partially replaces an expression by an already known result. In case the compiler would not do this it would anyhow create the same logic for the signal f. This cannot be the root cause of the "error due to feedback". Where is the feedback?