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Honored Contributor
Honored Contributorproblem with resource sharing.......
i've a piece of hardware which does something like this: a<= b xor c; d<= e xor b xor c; f<= g xor e xor b xor c; i do all these operations in 1 clk cycle....... but synthesizer do...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- i do all these operations in 1 clk cycle --- Quote End --- I seems, that you're doing the operations in no clock cycle, respectively in combinational logic. If so, the optimizations that you name resource sharing actually don't affect the logical behaviour. If the assignment would be performed in clocked process, the a result register is one clock behind the input term and could not replace it in another expression.
