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Altera_Forum's avatar
Altera_Forum
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17 years ago

problem with resource sharing.......

i've a piece of hardware which does something like this: a<= b xor c; d<= e xor b xor c; f<= g xor e xor b xor c; i do all these operations in 1 clk cycle....... but synthesizer do...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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i do all these operations in 1 clk cycle

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I seems, that you're doing the operations in no clock cycle, respectively in combinational logic. If so, the optimizations that you name resource sharing actually don't affect the logical behaviour.

If the assignment would be performed in clocked process, the a result register is one clock behind the input term and could not replace it in another expression.