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Altera_Forum
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16 years ago

Problem with PLL in EP1C12 device

Hello everyone, long time no see =] Recently I've built my own evaluation board with EP1C12 Cyclone device (yes, it's an old one, but I obtained it for free). The board is working, I can config...
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Altera_Forum
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16 years ago

The div_rst signal is active low. When the nrst signal is off (high) and PLL_lock signal is on (high) then div_rst is off (high), so no reset occurs. It's simple precaution against unexpected behavior of PLL before it's locked.