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Altera_Forum's avatar
Altera_Forum
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9 years ago

problem with pin placement for ddr2_dimm_clk[*]/clk_n[*]

I have a Stratix III dev kit and ran through the emi_tut_qdr.pdr External Memory tutorial just fine (https://www.altera.co.jp/ja_jp/pdfs/literature/hb/external-memory/emi_tut_qdr.pdf). This example design has an external memory interface and a few other peripherals. I am trying to create a hardware design that has external memory and a triple speed ethernet. I have set up Qsys with the external memory interface and other components (tse_mac, flash memory, sysid, etc) and followed the External Memory tutorial for all the steps on the external memory.

When I try to do a full compile of my design, I get the following errors:

Error (169291): Differential input pin ddr2_dimm_ck_n[1] is assigned to location AL13(PAD_305). However, the pin location does not support differential input.

Error (169291): Differential input pin ddr2_dimm_ck_n[2] is assigned to location AM15(PAD_301). However, the pin location does not support differential input.

Error (169291): Differential input pin ddr2_dimm_ck[1] is assigned to location AK13(PAD_304). However, the pin location does not support differential input.

Error (169291): Differential input pin ddr2_dimm_ck[2] is assigned to location AL15(PAD_300). However, the pin location does not support differential input.

I find these errors confusing because with the example design I used those same pins for those clocks, and those pins were set with the same differential standard as in this design (Differential 1.8-V SSTL Class I) but yet I get errors for this design.

I'm relatively new to FPGA, so any help/explanation would be greatly appreciated.

Erin

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    I put in a service request about this issue and the response from Altera was that those pins indeed do not support differential input because the pins for _ck[1]/_ck_n[1] and _ck[2]/_ck_n[2] are not on dedicated TxRx channels. My question is then why did these pin assignments work for the example design in emi_tut_qdr.pdf but not for this design? Also does the DDR2 DIMM need 3 clocks or would one clock be sufficient?

    Erin
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    I figured out that my issue was that the clocks pins to the external memory were set as bidirectional pins, but they should be output pins. I should have checked that top level file more closely and compared to the working external memory design that I have. (I got the file originally from the stratixIII_dev_niosII_standard design and then I modified it, but I failed to notice the issue with the clock pin directions.)