problem with pin placement for ddr2_dimm_clk[*]/clk_n[*]

I put in a service request about this issue and the response from Altera was that those pins indeed do not support differential input because the pins for _ck[1]/_ck_n[1] and _ck[2]/_ck_n[2] are not on dedicated TxRx channels. My question is then why did these pin assignments work for the example design in emi_tut_qdr.pdf but not for this design? Also does the DDR2 DIMM need 3 clocks or would one clock be sufficient?