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Altera_Forum
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9 years ago

problem with pin placement for ddr2_dimm_clk[*]/clk_n[*]

I have a Stratix III dev kit and ran through the emi_tut_qdr.pdr External Memory tutorial just fine (https://www.altera.co.jp/ja_jp/pdfs/literature/hb/external-memory/emi_tut_qdr.pdf). This example d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I figured out that my issue was that the clocks pins to the external memory were set as bidirectional pins, but they should be output pins. I should have checked that top level file more closely and compared to the working external memory design that I have. (I got the file originally from the stratixIII_dev_niosII_standard design and then I modified it, but I failed to notice the issue with the clock pin directions.)