problem with ModelSim

This error would imply that sumador has no architecture associated with its entity.

why are all your file extensions .vdh instead of the standard .vhd?

you also dont declare .vhd files as components, its the entity name thats important (usualy the same name as the filename).

Sorry the extension are vhd, here are the sources:

library ieee;

use std.textio.all;

entity bancopruebas is

end bancopruebas;

--

architecture estructura of bancopruebas is

signal OpA,OpB,suma:integer;

component sumador

port(OpA: in integer;

OpB: in integer;

suma : out integer);

end component;

begin --proceso que lee los estimulos y graba los resultados

process

constant Periodo :time:= 100 ns;

file Datos :text is in "Datos.txt";

variable lineadatos :line;

file resultados :text is out "resultados.txt";

variable linearesultados :line;

variable OpA_I,OpB_I :integer;

begin

while not endfile(Datos) loop

readline(Datos,lineadatos); --

read(lineadatos,OpA_I);

read(lineadatos,OpB_I);

OpA <= OpA_I;

OpB <= OpB_I;

wait for Periodo;

write(linearesultados,OpA);

if OpB_I < 0 then

write(linearesultados,string'("-"));

else

write(linearesultados,string'("+"));

end if;

write(linearesultados,abs(OpB));

write(linearesultados,string'("="));

write(linearesultados,suma);

writeline(resultados,linearesultados);

end loop;

wait;

end process;

-- Referencia al sumador

sumador0: sumador port map(OpA,OpB,suma);

end estructura;

---------------and the sumador is

entity sumador is

port(OpA : in integer;

OpB : in integer;

suma : out integer);

end sumador;

as you can see I dont need architecture here becouse the first program do the job

But you do need an architecture - the architecture defines how sumador works. Without one sumador doesnt exist.

The quickest way to fix it would be to comment out the sumador instantiation and the component or just add an empty architecture.

thank tricky , it work!!!! but not with the result I expected

I hve to check ...thank anyway....

:)

probably because you forgot the line:

suma <= OpA_I + OpB_I;

but even this is going to have your results lagging by 1 result because suma is a signal and not a variable.

once again you got the reason...

I put suma<=OpA + OpB in sumador' architecture and it work perfect

with the result that I expected.....

THANK A LOT TRICKY!!!!!!!!!!!!!!!!!!!