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Altera_Forum
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14 years ago

Problem with Gigabit Ethernet Clocks

Hi, I am working in a design that includes a propietary MAC layer to the PHY Marvell Ethernet chip, using RGMII interface. The FPGA that I used to the design is a ARRIA GX II 260. I have define...
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Altera_Forum
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14 years ago

Once the clocks are defined, you must ensure that all the I/O pins are constrained. There is one report called unconstrained paths that will tell you if some of the pins aren't constrained.

When applying the SDC rules, check that the pin names match the one of your design. If the RGMII pins are constrained, Timequest should then tell you if the timing requirements are met. If they aren't, you'll find the failing paths in the report "top failing paths"