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Altera_Forum's avatar
Altera_Forum
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17 years ago

Problem with flash programmer

Hi,

I am sure it is a beginner problem but I am not able to find an answer in the help of NiosII.

I would like to program my FPGA (http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html) with a .sof file.

So I create a new project hello_world with a niosII_stratixII_2s60\full_featured SOPC builder.

then I go to the flas progammer, I choose my project. Project and SOPC builder are recognized.

Then I select the box "Program FPGA configuration data into harware-image region of flash memory". I disselect "Program software project into flash memory).

I choose my .sof file

Then I choose my hardware Image, I have two choices: factory U5+0xC00000 or user: U5 + 0x800000.

I choose the second ( but it dosnt work with the 2 configurations).

I switch on my board,

Then I click on Program flash.

Building and conversion to flah file are OK.

then he tells me:

"#  Programming flash with the FPGA configuration
$SOPC_KIT_NIOS2/bin/nios2-flash-programmer --device=1 --sidp=0x021108C8 --id=203
2497071 --timestamp=1145613411 --base=0x00000000 full_featured.flash
There are no Nios II processors available which match the values specified.
Please check that your PLD is correctly configured, downloading a new SOF
file if necessary. "

I had a look to the ug_nios2_flash_programmer:

Probable Cause
The flash programmer is unable to connect with a Nios II JTAG debug
module inside the FPGA.
Suggested Actions
■ Make sure that the FPGA is running a valid flash programmer target
design. If not, you need to configure the FPGA using the Quartus II
programmer. See “Flash Programmer Target Design” on page 1–3.

What does that mean???

I had a look on page 1-3 and they say to use the full featured SOPC builder (as i did).

I have tried some others configurations but none allow me to go further than the config I have described.

Can someone help me ?

19 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Two concurrent programming methods have been discussed in this thread:

    1. Using Nios II Flash Programmer (which requires the EPCS serial flash controller module included to the NIOS II design and loaded previosly to the FPGA). Personally I'm not using NIOS II, so I can't give further hints regarding this method. See Nios II Flash Programmer User Guide for details.

    2.Using standard Quartus Programmer and jic file(which requires the said SFL IP included to the design and loaded previously to the FPGA). My comments have been related to this method. See AN370 http://www.altera.com/literature/an/an370.pdf
  • Altera_Forum's avatar
    Altera_Forum
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    I have followed step by step the AN370:

    -Conversion sof=>jic (with the compression, that is not mentionned in the an)

    -Generation of a SFL megafunction

    -Loading of the .jic

    This error remains when I try to load my .jic: error: can't recognize silicon id for device 1

    But I have a question about the SFL megafunction:

    When has the configuration been loaded to the FPGA in these step??

    I have generated a VHDL file ( and a .cmp) but I never used it...

    Or maybe it´s a malfunction case as you said in a previous post, but in this case I don´t know what else I can do...
  • Altera_Forum's avatar
    Altera_Forum
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    My blank SFL design looks like this

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    ENTITY sfl_3c16 IS
    END sfl_3c16;
    ARCHITECTURE RTL OF sfl_3c16 IS
    COMPONENT sfl
      PORT
      (
        noe_in		: IN STD_LOGIC
      );
    END COMPONENT;
    BEGIN
      sfl_inst : sfl PORT MAP (
      noe_in	 => '0'
      );
    END RTL;
  • Altera_Forum's avatar
    Altera_Forum
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    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    LIBRARY altera_mf;
    USE altera_mf.all;
    ENTITY sfl IS
    	PORT
    	(
    		noe_in		: IN STD_LOGIC 
    	);
    END sfl;
    ARCHITECTURE SYN OF sfl IS
    	COMPONENT altserial_flash_loader
    	GENERIC (
    		enable_shared_access		: STRING;
    		lpm_type		: STRING
    	);
    	PORT (
    			noe	: IN STD_LOGIC 
    	);
    	END COMPONENT;
    BEGIN
    	altserial_flash_loader_component : altserial_flash_loader
    	GENERIC MAP (
    		enable_shared_access => "OFF",
    		lpm_type => "altserial_flash_loader"
    	)
    	PORT MAP (
    		noe => noe_in
    	);
    END SYN;

    Not exactly the same... I am going to cut/paste your blank sfl, i will see
  • Altera_Forum's avatar
    Altera_Forum
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    Just a quick reset here:

    The original post stated you had a EP2S60 DSP kit and then you were using the Stratix II Nios II project as a starting point. The Stratix II Nios II development board is not the same as the Stratix II DSP kit even though they both use the EP2S60 device. One of the differences between the two boards is that the DSP kit doesn't even have an EPCS device on it. The DSP kit uses a bulk flash device and a CPLD to configure itself.

    I think you're going to have to create a simple Nios design with a parallel Flash Programmer and then create the JIC file to talk to that.
  • Altera_Forum's avatar
    Altera_Forum
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    Yes, the DSP Dev Kit is using a parallel flash rather than an EPCS, I wasn't aware of that fact. The standard PFL programming file would use a *.pof type instead of *.jic for serial flash loader, but I don't know what's the NIOS II flow.

  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    I think you're going to have to create a simple Nios design with a parallel Flash Programmer and then create the JIC file to talk to that.

    --- Quote End ---

    I have made a hello world project with a full_featured EP2S60F_ES device, launched ths Flah programmer, check the box "program FPGA configuration data into hardware image region of memory", uncheck all the others, choose my .sof file, chosen my hardware image (user:U5+0x800000).

    and I have this error:

    # Programming flash with the FPGA configuration
    $SOPC_KIT_NIOS2/bin/nios2-flash-programmer --sidp=0x021108C8 --id=2032497071 --t
    imestamp=1145613411 --base=0x00000000 training.flash
    There are no Nios II processors available which match the values specified.
    Please check that your PLD is correctly configured, downloading a new SOF
    file if necessary.

    ( EDIT: I have found a paralell flash loader in Plug in wizards, but it tolds me its not available with Stratix II, I can only chosse Serial flash loader)
  • Altera_Forum's avatar
    Altera_Forum
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    This is the answer of Altera support:

    --- Quote Start ---

    You need to design a project with Nios II processor and the flash memory. And then, compile this project in Quartus II and configure the FPGA by the generated sof file. After that, in Nios II IDE, you can program the sof in the flash memory by Nios II flash programmer.

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    Sometimes it is useful to check 'Halt onchip configuration controller' in Options --> Programmer if your serial flash is empty