Forum Discussion
Altera_Forum
Honored Contributor
17 years ago
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sfl IS
PORT
(
noe_in : IN STD_LOGIC
);
END sfl;
ARCHITECTURE SYN OF sfl IS
COMPONENT altserial_flash_loader
GENERIC (
enable_shared_access : STRING;
lpm_type : STRING
);
PORT (
noe : IN STD_LOGIC
);
END COMPONENT;
BEGIN
altserial_flash_loader_component : altserial_flash_loader
GENERIC MAP (
enable_shared_access => "OFF",
lpm_type => "altserial_flash_loader"
)
PORT MAP (
noe => noe_in
);
END SYN; Not exactly the same... I am going to cut/paste your blank sfl, i will see