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Altera_Forum's avatar
Altera_Forum
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18 years ago

Problem with flash programmer

Hi, I am sure it is a beginner problem but I am not able to find an answer in the help of NiosII. I would like to program my FPGA (http://www.altera.com/products/devkits/altera/kit-dsp-...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

My blank SFL design looks like this 

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sfl_3c16 IS
END sfl_3c16;
ARCHITECTURE RTL OF sfl_3c16 IS
COMPONENT sfl
  PORT
  (
    noe_in		: IN STD_LOGIC
  );
END COMPONENT;
BEGIN
  sfl_inst : sfl PORT MAP (
  noe_in	 => '0'
  );
END RTL;