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Altera_Forum's avatar
Altera_Forum
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15 years ago

problem with cyclone III and jtag

I would like to put a very serious discussion about using jtag with cyclone III.

has cyclone3 less electrical tolerance compared to other FPGA's??????

. we are building a custom board. and to my horror 2 of them have suddenly stopped to down load .sof. Till yesterday every thing was fine, but when i started to work today i find them unable to detect jtag chain.

My jtag cable is from terasic. I have used the same schematic as given in altera configuration handbook for cyclone3. I am configuring the FPGA in AS well as in jtag mode. I'm able to download .pof.

After reading so many posts regarding jtag and cyclone3, I am in confusion wether the FPGA has gone bad or the jtag.

Is there any special protection that needs to be taken when using cyclone3 with Jtag.

Kindly help its very urgent. Can anyone plz provide a schematic for interfacing jtag with cyclone3.

regards

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It isn't a problem at all. I usually do that when I have enough space on the board. It makes the board more tolerant and offers more protection on the FPGA JTAG pins. If you put the buffer close to the FPGA you don't have to worry about overshoots.

    Just be sure to select a buffer that is fast enough for the JTAG signals. I use a SN74LVC541A, and it works very well. All the JTAG signals go through the buffer.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I am implementing a connection as shown in the following reference which shows programming a serial device through JTAG:

    Figure 9-30 on page 60 of cyc3_ciii51016-2.pdf

    We are using the USB-Blaster cable. I've inserted the 74LVC541 between the connector and the FPGA for the 4 JTAG signals. Pin6 of the JTAG 10 pin connector is a No Connect and Pin 4 is connected to VCCA 2.5V. The pull ups for TDI and TMS are to VCCA 2.5V. Our cycloneIII is configured such that B1 is 3.3V which contains the JTAG signals. The nCONFIG and nSTATUS signals are pulled up as they are in the above reference to VCCIO1(3.3V). The CONF_DONE signal is in B6 and is pulled up to VCCIO6 of 1.5V.

    All other connections are exactly as shown in the reference above. Does this capture all your recommendations on how to ensure the FPGA is protected? Did I miss something?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It should be good. Just check that the 74LVC541 is powered by a 2.5V supply (or if you power it with 3.3V, put also 3.3V on the Jtag pin 4) and that the pull ups/down are between the JTAG connector and the buffer, and not between the buffer and the FPGA.