Forum Discussion
Altera_Forum
Honored Contributor
15 years agoWhat voltage are you using for the JTAG interface? There is an issue when you use 3.0 or 3.3V for the Jtag signals, if you don't add external clamping diodes. If an overshoot voltage goes over 4.1V it can destroy the I/O buffer of the FPGA.
Usually if I have the space I put a buffer on the PCB between the FPGA and the JTAG connector, for protection.