--- Quote Start ---
your input P is 7, so the q value takes 7 as the active low load signal loads it.
There are many redundant lines in your code. you never need to assign count_sig to itself.
Here is a much tidier version of your code. I have removed the asynchronous enable because you want to use it synchronously:
begin
process (clk, MR, p_load, p)
begin
if (MR='1') then
count_sig <= "00000";
elsif (p_load='0') then
count_sig <= unsigned(p);
elsif rising_edge(clk) then
if EN = '1' then
case UP_DW is
when '1'=>count_sig<=count_sig +1;
when '0'=>count_sig<=count_sig -1;
when others => count_sig <= "XXXXX";
end case;
end if;
end if;
end process;
q<= std_logic_vector (count_sig);
end flow;
--- Quote End ---
I just tried this code just now. However it still can't give the graph of the expected outcome.
Honored Contributor
