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Altera_Forum's avatar
Altera_Forum
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13 years ago

Problem using ISSI's SRAM on Stratix IV GX

Hello everyone.

Anyone had luck using the SSRAM provided on a Stratix IV GX Dev Kit (EP4SGX230KF40C2ES)?

I think there is a huge lack of information by Altera by using this SSRAM module, on altera website, we can only find tutorials related to the QDRII+ memory.

I'm using Qsys to integrate the SSRAM to a NIOS CPU, and I've tried to use the generic tri-state controller with the closest preset available (another ISSI module), and had no luck. The system compiles, and the NIOS EDS recognizes the CPU, starts to upload the elf program, and then fails at verification ("Verify failed between addresses...").

I have double checked all my pins:

QSYS OUTPUT PIN -> CONNECTED PIN

sram_tcm_chipselect_n_out -> sram_cen

sram_tcm_byteenable_n_out[3..0] -> sram_bwn[3..0]

sram_tcm_outputenable_n_out -> sram_oen

sram_tcm_write_n_out -> sram_bwn

sram_tcm_data_out[31..0] -> fsm_d[31..0]

sram_tcm_address_out[20..0] -> fsm_a[20..0]

sram_tcm_reset_n_out -> ?

sram_tcm_begintransfer_n_out -> sram_adscn

anyone can give me a light? thank you!

15 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hello,

    The verification failed between which addresses?

    Could you give/print us the "Address Map" of your Qsys System please?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    What are the clock frequencies in the clock source and pll?

    Print the configuration of the two tri-state component.

    Did you set yourself the addresses in Qsys?

    I think yes, try "Assign base addresses" in System in the toolbar of Qsys, save the Qsys system, re-compile and upload the .elf .
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    running the memory test provived on NIOS EDS from a on-chip memory on the SRAM gives me the following output:

    Testing RAM from 0x200000 to 0x3FFFFF

    -Data Bus test passed

    -Address bus test failed at address 0x200004

    Press enter to continue...
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    -Data Bus test passed

    -Address bus test failed at address 0x200004

    --- Quote End ---

    It looks like the test software is able to write different values to the first address, but not the second one. Can you check in the pin planner that the fsm_a[20..0] ports are assigned to the correct FPGA pins? Verify using the board's schematic. (the user documentation can be wrong sometimes)
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The pins are correct, according to reference manual and the pinning script (golden_top.tcl) provided on the devkit cd-rom.

    To map 2MB using words of 32-bits, should I use 19 or 21 bits for addressing? I saw on reference manual that they exclude the two first pins for addressing, fsm_a[0] and fsm_a[1], which I have correctly pinned using the pinning script.

    Anyway, thanks for the help folks!
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    After weeks of suffering, the problem is finally solved!

    I resetted the parameters of the generic tri-state controller to cypress's defaults, fed up the whole circuit with a clock of 50 MHz coming from a PLL, and exported a second clock from this PLL on 50Mhz with a phase shift of -2.03 ns, and connected this shifted clock to the sram clock, and it passed on all tests!

    I have based my results on a very hidden project using SRAM on the devkit cd-rom, on this project, the used clock is 83.333333 MHz, with a phase shift of -3.38ns.

    Thanks for everyone who helped me!
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    It's good to know you pass the test now!

    Did you constrain the SRAM interface in Timequest with the memory's setup and hold requirements? Because if you had a clock that wasn't properly aligned it would probably have been picked up by Timequest.

    If you are not familiar with Timequest yet, you can read this user guide (http://www.alterawiki.com/wiki/timequest_user_guide) on the wiki.