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Altera_Forum
Honored Contributor
13 years agoAfter weeks of suffering, the problem is finally solved!
I resetted the parameters of the generic tri-state controller to cypress's defaults, fed up the whole circuit with a clock of 50 MHz coming from a PLL, and exported a second clock from this PLL on 50Mhz with a phase shift of -2.03 ns, and connected this shifted clock to the sram clock, and it passed on all tests! I have based my results on a very hidden project using SRAM on the devkit cd-rom, on this project, the used clock is 83.333333 MHz, with a phase shift of -3.38ns. Thanks for everyone who helped me!