Honored Contributor
Honored ContributorI wouldn't have reported the solution, if it doesn't work.
I append the basic code for the LVDS receiver. Please consider, that I didn't spend any effort to make a parameterizable module with documented timing parameters, the slow- and fastclock phases have been set by empirical measurements and tests. The clock source PLL isn't absolutely necessary, respectively an additional output of an existing PLL can be used. If the ADC clock is identical with the aplication main clock (32 MHz in this case) you have a good chance to use the received data without explicite synchronisation. The receiver structure is basically usable for any even serialisation factor. As an additional comment. Cause Cyclone III has a dynamic phase shift option with PLLs, there is an interesting option to calibrate the receiver automaticly utilizing the ADC test pattern. This would be particularly interesting for applications operating nearer to the LVDS frequency limits. Regards, Frank
