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Altera_Forum's avatar
Altera_Forum
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17 years ago

problem using cyclone ep1c3t144

Hello, guys i have a problem and i would like to discuss it with you,

I have designed a pcb which has a 10bit ADC and sends LVDS signals to ALTERA's EP1c3t144, the problem is the following , i use alt_lvds_rx inside altera and at the output i have something like a phase shift (i.e. i send a standard bit pattern from adc 0001011101 MSB->LSB and on the output pins of altera i see 0100010111. I checked the input( i declare the input (p) as lvds signal in quartus II) from an oscilloscope and i see that the right bit pattern arrives in the altera. I have tried to use external PLL in the alt_lvds_rx fuction and put a seperate pll but nothing happened

Also i tried to add a phase shift but nothing happened:o. Has anyone have any ideas of what is going on here? I use a clock of 30 Mhz( i have lowered it in order to see what is happening i want to go up to 240 Mhz) as input clock in the alt_lvds(or at external pll) and i use the frame that is an lvds signal (output of the adc) to feed the clock of a d Flip flop in the output of the alt_lvds_rx.

PLEASE HELP

thank you all.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Your asking, how to correct the receiver phase to be alligned with your LVDS signal?

    It seem to me that, the lvds-receiver Megafunction has an undocumented systematic phase shift, that is inappropriate for cyclone design, e. g. when receiving from an Analog or TI LVDS ADC. I remember, that I once had some problems with it. In one case, I finally ended up in using a custom LVDS receiver based on altddio_in and a shift register. This also allowed me the straightforward definition of a 14 bit receiver, that isn't supported by the Megafunction for arbitrary reasons.

    With the lvds receiver Megafunction, your basically able to setup any phase by setting the phase shift for the slow clock accordingly. But a correct setting isn't always provided by the Megawizard.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    thanx for replying, You said that"""In one case, I finally ended up in using a custom LVDS receiver based on altddio_in and a shift register"" you mean that you have made a modified programm in vhdl for altddio_in? and you also put a shift register? did it work?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I wouldn't have reported the solution, if it doesn't work.

    I append the basic code for the LVDS receiver. Please consider, that I didn't spend any effort to make a parameterizable module with documented timing parameters, the slow- and fastclock phases have been set by empirical measurements and tests. The clock source PLL isn't absolutely necessary, respectively an additional output of an existing PLL can be used.

    If the ADC clock is identical with the aplication main clock (32 MHz in this case) you have a good chance to use the received data without explicite synchronisation.

    The receiver structure is basically usable for any even serialisation factor.

    As an additional comment. Cause Cyclone III has a dynamic phase shift option with PLLs, there is an interesting option to calibrate the receiver automaticly utilizing the ADC test pattern. This would be particularly interesting for applications operating nearer to the LVDS frequency limits.

    Regards,

    Frank