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I have to be able to shutdown a clock to different sections of logic for power saving purposes. I generate this clock via a pll from a master input clock. I then need to run this clock to 6 altclkctrl blocks to selectively enable/disable this clock to various sections of logic.
The logic blocks are part of a large pipeline and data flows thru them, depending on which clocks are enabled. I can't split up the pll that generates this clock into 6 different plls as I'm pretty much out of plls in the chip.
When I synthesize, I get an error that basically says "Can't place node clk0 (pll output). Requires 7 clock signals which exceeds max of 6."
Does anybody have any ideas or has dealt with this type of situation before?
The device is a Stratix2.
Thanks.
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Hi,
can you post a drawing or project in the forum ?
Kind regards
GPK
Honored Contributor
