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Altera_Forum
Honored Contributor
18 years agoproblem using altclkctrl...any suggestions
I have to be able to shutdown a clock to different sections of logic for power saving purposes. I generate this clock via a pll from a master input clock. I then need to run this clock to 6 altclkc...
Altera_Forum
Honored Contributor
17 years agoUnfortunately, I can't remember what I did there. I think the customer for the design went belly up in terms of funding so we never had to find a solution to that issue.
If I free up some time, I'll go back thru my notes to verify that's what happened. Having to generate many clocks in the fpga and then trying to add shutdown capability is a problem in terms of resources. Sorry I couldn't be more help.