Problem simulating FIFO at Modelsim

What kind of HDL you mean?

module fifowrapper(
                    // inputs:
                     rdclk,
                            rstn,
                            rdreq,
                    // outputs:
                     valid,
                     q
                  );
                        
input  rdclk;
input rdreq;
input rstn;
reg rdreqtemp;
reg wrclk;
reg wrreq;
output  q;
output reg valid;
wire  data;
reg  data_in;
assign data = data_in;
wire  usedw;
reg  contador;
reg  delay;
always@(posedge rdclk or negedge rstn)
  if (~rstn)
   begin
   valid <= 0;
   contador <= 0;
   data_in <= 0;
   wrreq <= 0;
    delay <= 0;
   end
  else
begin
        contador <= contador +1;
        valid <= 0;
        wrreq <= 0;
           if(usedw == 6'b100000)
            begin
                valid <= 1;
            end
            if(contador == 100000000)
            begin
                wrreq <=1;
                data_in <= data_in + 32'b00000000000000000000000000000001;
                contador <= 0;
            end
end
base    fifo_inst (
    .data ( data ),
    .rdclk ( rdclk ),
    .rdreq ( rdreq ),
    .wrclk ( rdclk ),
    .wrreq ( wrreq ),
    .q ( q ),
//    .rdempty ( rdempty_sig ),
//    .rdusedw ( usedw )
    .wrusedw ( usedw )
//    .wrfull ( wrfull_sig )
    );
endmodule

 `timescale 1 ns/1 ns
module tb_fifo;
parameter P_CLKPERIOD = 50;
reg tb_i_clk;
reg tb_i_rstn;
wire tb_valor;
//CLOCK DO SISTEMA EM 50ns - 20Mhz
initial tb_i_clk = 1'b1;
always# (P_CLKPERIOD/2) tb_i_clk <= ~tb_i_clk;
// RESET DO SISTEMA
initial
begin 
    @(posedge tb_i_clk);
    tb_i_rstn <= 0;
   # 10;
    @(posedge tb_i_clk);
    tb_i_rstn <= 1;
end
// BLOCO PRINCIPAL
fifowrapper u0(
    .rdclk (tb_i_clk),
    .rstn (tb_i_rstn),
    // outputs:
    .valid(tb_valor)
    //.q
    );
endmodule