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Altera_Forum's avatar
Altera_Forum
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16 years ago

Problem in using DDR

Hello everyone,

I have a problem in using ddr on Cyclone III starter kit.When I have compiled the design,it failed at the fitter with this error notification.

Error: can't place pin mem_dqs[1] to location T8.

can't place VREF pin T6 (VREFGROUP_B3_N0) for pin mem_dqs[1] of type bidirectional with SSTL-2 Class I / o standard at location t8.

can anyone help me please?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I face this problem before. You have to do some setting because there is too much bidir pins for 1 Vref.:)

    1st :

    Assigment-Device-Device and Pins option-Dual purpose pins(set all value to: use as regular I/O accept for DClock&nCEO.

    2nd :

    Assigment-Assigment Editor- Change all DQ,DQS and DM pins to (Output Enable Group). For the Value column, set any number same for those pins.

    eg: DQ[0]->Output Enable Group->123456(Value)

    3rd :

    Assigment-Pins(Change IO standard for all DDR related pins to SSTL-2 Class I.)

    You now are able to compile without any fail hopefully. I face this before and want to help you.:o

    Thank you:

    Shahril
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    You are welcome. Just want to ask, is it currently you also work on DDR memory? It will be great if we can work together. I just want to store a series of data inside DDR SDRAM. Is it you already start to do the software part? :o