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EquansAltera's avatar
EquansAltera
Icon for New Contributor rankNew Contributor
4 years ago
Solved

Problem for programing MAX7000

Hello,

I have electronic cards with 4 MAX7000 FPGAs which work perfectly and which I can program without any problem.

The 4 FPGAs are in a JTAG link (TDI-TDO) the first 3 are MAX7128S and the last a MAX7256S.

They were developed under Max+plus.

I program them with Quartus II programmer version 6.0 software and the Blaster USB interface.

I made a minor modification on the MAX7256S and regenerated a .POF file.

When I put the latest .POF file in the chain instead of the old one, I can no longer "verify" any of the FPGAs. I have an error message:

Error: Can't verify device and

Error: Operation failed

Whereas with the old POF file we can verify any FPGA.

The problem seems to be related to the newly compiled file?

Thank you for your ideas.

  • EquansAltera's avatar
    EquansAltera
    3 years ago

    I understood what is wrong.

    In fact, it is the verification part of the programmer that is buggy or illogical in its operation.

    I spotted two flaws:

    To check any fpga in the chain, there must be at least the first .pof file in the chain in addition to the .pof file to be checked.

    But it's not this weird thing that blocked me. To do a check of any fpga in the chain all .pof files, if put in the chain must be equal to what is in the fpgas on the card, even if it is not the one that we want to check. Because in this case the programmer does not even try to launch a verification and that is what stopped me, so much I wanted to understand.

    The solution is very simple, you can compile with any version, anything, you must first not try to check anything and simply start programming.

5 Replies

  • ak6dn's avatar
    ak6dn
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    So if you take the ORIGINAL, unmodified MAX7256S device and re-generate the POF file using Quartus 6.0, can that verify correctly?

    Or, can you re-program the MAX7256S using the re-gnerated POF file, and does that then verify?

    Quartus 6.0 is pretty old. Intel has just re-enabled the download of QuartusII Web 13.0sp1, which was the LAST version to support the MAX7K/3K series. I use 13.0sp1 on my test boards with MAX7264S/128S devices all the time. Works fine under Windows 7 64b and Windows 10 64b.

    • EquansAltera's avatar
      EquansAltera
      Icon for New Contributor rankNew Contributor
      4 years ago

      Hi,

      Thank you for your ideas.

      I did not try to regenerate a .pof without modifying anything to see if I could do a verify because modifying .pof already prevents doing a verify on other FPGAs.

      I concluded that the problem was in the format of the .pof file and not in its content.

      But I'll try anyway.

      I will also try the second idea, but until the string is not recognized with the new .pof, I don't believe it.

      The Quartus 6.0 is the programmer, for compilation i have the 9.1 version.

      I find it hard to believe that a somewhat old version is not compatible with the old Max and that 10 years later Quartus would have corrected an incompatibility on something that nobody uses anymore. For me if there had been a correction it would have been in the first versions, when people were still using the Max.

      Although my machines cannot be connected to the network I will see if I can upgrade the versions

      Thank you, I think I have a lot of work to do all this.

      I would have liked a simple checkbox

      Best Regards

  • ak6dn's avatar
    ak6dn
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Theoretically if nothing in your development environment has changed (like PC OS version, Quartus version, etc) it should still work.

    You don't mention anything about the software platform you are using. Windows?

    What source language is your device code in? AHDL? Verilog? VHDL?

    I do my MAX7K development on Windows 10 64b 21H1 with Quartus Web 13.0sp1 installed. My source is all in verilog.

    I can compile, program, verify using a USB-Blaster clone (I use the Terasic Blaster, it is a clone of the Altera USB Blaster but much less expensive).

    Never had a problem programming MAX7xxxS, MAX3xxx in this setup.

    Before changing any of your source code, I would think you would like to be able to regenerate the existing device POFs and verify.

    That would be my approach. Once that works, then start tweaking the code as required.

  • EquansAltera's avatar
    EquansAltera
    Icon for New Contributor rankNew Contributor
    4 years ago

    Precisely, 20 years ago I used Max+plus on W98.

    Now I'm on Quartus and XP, W7 and W10.

    And I also use the Terasic Blaster USB which works very well on all my boards with one or more Altera Max7000 FPGAs in a chain.

    I also have an Altera USB Blaster which only works on boards with a single FPGA.

    I will follow what you suggest, and I will see.

    • EquansAltera's avatar
      EquansAltera
      Icon for New Contributor rankNew Contributor
      3 years ago

      I understood what is wrong.

      In fact, it is the verification part of the programmer that is buggy or illogical in its operation.

      I spotted two flaws:

      To check any fpga in the chain, there must be at least the first .pof file in the chain in addition to the .pof file to be checked.

      But it's not this weird thing that blocked me. To do a check of any fpga in the chain all .pof files, if put in the chain must be equal to what is in the fpgas on the card, even if it is not the one that we want to check. Because in this case the programmer does not even try to launch a verification and that is what stopped me, so much I wanted to understand.

      The solution is very simple, you can compile with any version, anything, you must first not try to check anything and simply start programming.