Forum Discussion
New ContributorProblem for programing MAX7000
I understood what is wrong.
In fact, it is the verification part of the programmer that is buggy or illogical in its operation.
I spotted two flaws:
To check any fpga in the chain, there must be at least the first .pof file in the chain in addition to the .pof file to be checked.
But it's not this weird thing that blocked me. To do a check of any fpga in the chain all .pof files, if put in the chain must be equal to what is in the fpgas on the card, even if it is not the one that we want to check. Because in this case the programmer does not even try to launch a verification and that is what stopped me, so much I wanted to understand.
The solution is very simple, you can compile with any version, anything, you must first not try to check anything and simply start programming.
Regular ContributorTheoretically if nothing in your development environment has changed (like PC OS version, Quartus version, etc) it should still work.
You don't mention anything about the software platform you are using. Windows?
What source language is your device code in? AHDL? Verilog? VHDL?
I do my MAX7K development on Windows 10 64b 21H1 with Quartus Web 13.0sp1 installed. My source is all in verilog.
I can compile, program, verify using a USB-Blaster clone (I use the Terasic Blaster, it is a clone of the Altera USB Blaster but much less expensive).
Never had a problem programming MAX7xxxS, MAX3xxx in this setup.
Before changing any of your source code, I would think you would like to be able to regenerate the existing device POFs and verify.
That would be my approach. Once that works, then start tweaking the code as required.
