Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Problem delay

I have some problems with a project. In my project there are more inverter chained (chain of inverters). During the compilation, the sinthesis consider only one inverter if the inverters are odd...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

No. An LCELL states that that point is the output of a logic cell. If you feed it an AND gate, then it gets absorbed into that LUT and the LCELL is still the output.