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Honored Contributor
Honored ContributorProblem delay
I have some problems with a project. In my project there are more inverter chained (chain of inverters). During the compilation, the sinthesis consider only one inverter if the inverters are odd...
Altera_ForumHonored Contributor
Honored ContributorYes, i'm doing a ring oscillator. I have solved the problem with Lcell and i declare every single inverter with lcell.
The problem is that Lcell have 1 input and i want to declare also other logic gate (ex. and2, or2 etc) as Lcell. In this way i need 2 lcell to declare a single and2 gate. Is it true?
