Problem delay

Yep. Synthesis reduces logic that doesn't affect the RTL behavior. (This is usually a good thing, and when you don't want it done, you're usually doing a "non-standard" design.) You probably already know that, and there are cases where a ring-oscillator will do the job. (I've done a similar design but put an LCELL primitive after each NOT gate. This is easier in schematic, where thepancakes is better in HDL.

Make sure you time it correctly, which is difficult since it's not a synchronous structure, and the whole concept of static timing analysis is based on synchronous clocks. You may already know this, but there are slow and fast timing models, and your ring oscillator will be anywhere in between. So if the ring delay is 10ns in the slow model, it might be 5ns in the fast model. That means your loop delay is varying between 100MHz and 200MHz(half that for a full clock period). This is why uncalibrated ring oscillators are not used very often.