Problem delay

even though its dirty, i have done this in VHDL using the keep attribute:

library ieee;
use ieee.std_logic_1164.all;
entity keeplogic is
    port(
        insig         : in        std_logic;
        outsig         : out        std_logic;
        outkeep        : out        std_logic
        );
end keeplogic;
architecture rtl of keeplogic is        
signal sig_wire        :            std_logic;
signal keep1_wire    :            std_logic;
signal keep2_wire    :            std_logic;
signal keep3_wire    :            std_logic;
signal keep4_wire    :            std_logic;
signal keep5_wire    :            std_logic;
signal keep6_wire    :            std_logic;
attribute keep: boolean;
attribute keep of keep1_wire: signal is true;
attribute keep of keep2_wire: signal is true;
attribute keep of keep3_wire: signal is true;
attribute keep of keep4_wire: signal is true;
attribute keep of keep5_wire: signal is true;
attribute keep of keep6_wire: signal is true;
begin
    --does not preserve not gates
    sig_wire <= not( not( not( not( not (not insig)))));
    
    --does preserve not gates
    keep1_wire <= not insig;
    keep2_wire <= not keep1_wire;
    keep3_wire <= not keep2_wire;
    keep4_wire <= not keep3_wire;
    keep5_wire <= not keep4_wire;
    keep6_wire <= not keep5_wire;
    
    outsig <= sig_wire;
    outkeep <= keep6_wire;
end;