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Altera_Forum's avatar
Altera_Forum
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10 years ago

Probing signals of MAX V CPLD

Hi,

I am working on MAX V CPLD and I require to probe some of the signals of CPLD.

I have come to know that I cannot use signal tap analyzer as it requires on chip RAM.

How can I go about debugging my design?

Thank you

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    Hi,

    How can I go about debugging my design?

    Thank you

    --- Quote End ---

    On These devices as also FvM sai'd, you need an external interface to route signal at a probe connected IE to a real logic analyser.

    On my old designs to debug I was providing a connector matching Agilent probe to connect painless.