Probing signals of MAX V CPLD

Question

Hi,

I am working on MAX V CPLD and I require to probe some of the signals of CPLD.

I have come to know that I cannot use signal tap analyzer as it requires on chip RAM.

How can I go about debugging my design?

Thank you

altera_forum · Answer

You can use Source &amp; Probe.

altera_forum · Answer

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Hi,

How can I go about debugging my design?

Thank you

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On These devices as also FvM sai'd, you need an external interface to route signal at a probe connected IE to a real logic analyser.

On my old designs to debug I was providing a connector matching Agilent probe to connect painless.

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