You cound take a look at the "absolute maximum" and "maximum specified" current / voltage ratings for the power supply rails as well as the signal set groups and the individual miscellaneous pins. You'll probably find that the group level or absolute maximum device level limits are limiting moreso than the sum of all possible currents / voltages and dynamic power consumption figures were the device to be 100% active in static and dynamic current consumption including every I/O sourcing/sinking maximum current simultaneously.
If your power solution can deliver enough to give absolute maximum and maximum recommended power levels to the chips, and you include enough extra for other power using devices on the PCB, and add some reasonable extra margin, you're all set.
Also look at the application notes concerning power supply design solutions for the chip and chip family in question; I know Altera and Linear Technology have various application notes and reference designs which will be informative. I believe that the schematics and PCB layouts for several Altera designed development boards are available for download, so you can probably learn what they considered to be a reasonably capable power solution and layout from those.
Of course since it is a dev. board, you're well advised to over design the safety and supervision circuits and power system capacity according to what possible accidents could be envisioned such as short circuits, ESD hits, accidental output driving conflicts due to programming / wiring errors, input overvoltages, et. al.
Since you're using a small device, you'll probably find that whatever is used on the higher capacity dev. board reference designs using the same series / generation of IC will provide ample power for your PCB, though if you're going to reuse those designs, ensure that you recalibrate anything necessary so a load only a fraction of the "nominal design value" will not result in regulation failure since sometimes there are minimum load requirements too.
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