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Honored ContributorPower saving techniques for FPGA
Hi,
Can someone share experence about power saving in FPGA designs? I am facing power consumption and heat disipation problems. I tried disabling clocks but that gives very litle diference in power consumption. What else could be done to reduce power consumption?3 Replies
Altera_ForumIt is not easy to optimize for power. Perhaps for a start you can check against the EPE to have an idea of static vs dynamic power distribution - just to estimate the potential reduction that can be done on the dynamic side. For static, if you device supports it, turn on the PowerPlay power optimization to normal/extra effort. Then, on the programmable power technology optimization, select the one that fits your design requirement.
- Altera_Forum--- Quote Start --- It is not easy to optimize for power. Perhaps for a start you can check against the EPE to have an idea of static vs dynamic power distribution - just to estimate the potential reduction that can be done on the dynamic side. For static, if you device supports it, turn on the PowerPlay power optimization to normal/extra effort. Then, on the programmable power technology optimization, select the one that fits your design requirement. --- Quote End --- Can you provide any hint on where to start with EPE? I have never used it.
- Altera_Forum--- Quote Start --- Can you provide any hint on where to start with EPE? I have never used it. --- Quote End --- https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_epe.pdf Use Processing->PowerPlay Power Analyzer Tool to write a EPE file, which you then import to the spreadsheet so you can play with "what if" scenarios.
