Honored ContributorHi,
Can someone share experence about power saving in FPGA designs? I am facing power consumption and heat disipation problems. I tried disabling clocks but that gives very litle diference in power consumption. What else could be done to reduce power consumption?
Honored ContributorIt is not easy to optimize for power. Perhaps for a start you can check against the EPE to have an idea of static vs dynamic power distribution - just to estimate the potential reduction that can be done on the dynamic side. For static, if you device supports it, turn on the PowerPlay power optimization to normal/extra effort. Then, on the programmable power technology optimization, select the one that fits your design requirement.
Honored ContributorHonored Contributor
