Forum Discussion

Honored Contributor

9 years ago

Power saving techniques for FPGA

Hi, Can someone share experence about power saving in FPGA designs? I am facing power consumption and heat disipation problems. I tried disabling clocks but that gives very litle diference ...

Altera_Forum

Honored Contributor

9 years ago

--- Quote Start ---

Can you provide any hint on where to start with EPE? I have never used it.

--- Quote End ---

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_epe.pdf

Use Processing->PowerPlay Power Analyzer Tool to write a EPE file, which you then import to the spreadsheet so you can play with "what if" scenarios.

Forum Discussion

Power saving techniques for FPGA

Recent Discussions

Request for COO info

JTAG Chain Broken on Agilex 7-I Dev Kit

Feasibility to implement 350MHz LVDS + soft-CDR on Cyclone 10LP

Question

Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?