Power on detection

Hello, please help me solving the issue.

I have FPGA (cyclone-3 based) module connected to another system. That system generates reset signal on power on, and FPGA translates this signal to its devices. But it did not work some times, and I found out why: when power is applied, system activates reset signal, at the same time FPGA starts configuration from EPCS device. However, it seems configuration takes longer than system has reset signal active, and when FPGA is "ready" reset time has already finished, and devices attached to FPGA were not reset properly ("reset" output pin of FPGA was tri-stated during config).

Of course there's option to solve it in hardware - put pull-down resistor onto FPGA "reset" output pin, and during configuration all devices will be in reset state.

Is there any way to solve this issue in FPGA configuration - e.g. detect the end of configuration so that FPGA can perform reset to its attached devices?

Please advise. Thank you!