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Altera_Forum
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10 years ago

Power on detection

Hello, please help me solving the issue. I have FPGA (cyclone-3 based) module connected to another system. That system generates reset signal on power on, and FPGA translates this signal to its...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Are you questioning why the pin is high during configuration? Read about configuration in the Cyclone III device handbook. It clearly states that all I/O pins are tristated with weak internal pull-ups until until configuration is complete. The pull-ups cannot be disabled, so if you need an FPGA pin to be held low prior to and during configuration you have to add an external pull-down resistor.