Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Power on detection

Hello, please help me solving the issue. I have FPGA (cyclone-3 based) module connected to another system. That system generates reset signal on power on, and FPGA translates this signal to its...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thank you. With 2.7kOhm it should achieve 0.32V, with 1.2mA drain when line is brought high. Should be OK for 3V3 LVTTL.

Edit: tested, after power up and during configuration pin now has low level.