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KJ's avatar
KJ
Icon for New Contributor rankNew Contributor
1 day ago

Power and thermal characterization of Agilex 5

We are working on the power characterization of a design based on the Agilex5 E-series and I've come across a few questions I haven't been able to fully resolve from Altera's documentation. Would you...
Power
Farabi_Altera's avatar
Farabi_Altera
Icon for Regular Contributor rankRegular Contributor
2 hours ago

Hello Chris, 

 

1- Typical static power model

i- When the typical static power model will be available? 

Ans: Please refer here Table 23

 

ii- access to pre-release model 

Ans: All the E-series power model is updated in 26.1

 

2- Power and Thermal Analyzer on empty design

i(a)- design use no DSP or RAM blocks

Ans: This is expected. Even no DSP or M20K blocks instantiated, the silicon physically contributes leakage/static power. 

 

i(b)- Which fabric component draw power significantly

Ans: clock input buffer, Global clock, configuration related circuitry, SDM, default termination, unused IO bank static leakage etc.IO is only one part of the contributors.

 

i(c) - what is included in miscellaneous category?

Ans:  SDM related circuit, Configuration circuit, Device management logic, power-monitoring circuit(POR), temperature/voltage sensing circuit, etc.

 

3- Can HPS and transceivers by fully powered down by disconnecting the power rails?

Ans: Basically yes, but why? you can choose device variance without HPS and without transceiver if you dont want this feature. This variance comes without HPS and transceivers. 

 

regards,
Farabi