Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Possible to call verilog code from a c program running on a soft processor on an FPGA

I have a soft NIOS II processor instantiated on an Altera FPGA. I have 4 JTAG pins connected from the FPGA to a FTDI chip (lets call them A1, A2, A3, A4). I have the JTAG pins from 2 MCUs connected t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

FPGA JTAG pins are dedicated resources with fixed location and can't be selected by configuration or user logic.

FPGA logic blocks aren't "called", neither from other FPGA modules nor a soft processor. The logic operation can be however made conditional, depending on a register written by the soft processor.