Honored Contributor
Honored Contributor- Open your VHDL file in Quartus, then go to Edit -> Insert Template -> VHDL -> Synthesis Attributes. You'll see one called useioff(or something like that).
- To be honest, I never see Altera users doing this. The OLD way Altera users did this was in the Assignment Editor. You would select the I/O port name in the To column, and then assign Fast Input Register, Fast Ouput Register and/or Fast OE Register. - The recommended method is to have timing constraints on your I/O. The fitter will automatically put registers into the I/O cell to meet timing requirements, but can do other stuff too, like pull it out of the register if that would help timing(or if it is necessary to balance paths to the fabric). Now, I understand some slow interfaces are annoying to enter timing constraints, and the general feeling is if an I/O register is used it will always meet timing. This isn't fullproof, but works most of the time, so it's really up to you.
