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Altera_Forum
Honored Contributor
Honored ContributorPorting VHDl code to processor blocks
Hello all,
I have the basic components of a VHDL implementation of a jpeg encoder (ZZ, DCT etc.) and am looking for ideas to port this onto (simulated) processor blocks. I have seen a lot of implementation ideas but no concrete implementation. I am familiar with the Xilinx tool and played around with simple mappings but am having some difficulty in mapping to control units and the like. Are there any books/tutorials available which will give me a detailed idea of how to map the code blocks to processor blocks ? I am not looking for mapping for my specific components but any implementation of VHDL blocks to hardware would be a great help. Thanks !5 Replies
Altera_ForumIm not quite sure what you're asking. If you have the VHDL, why cant you just compile the VHDL - or is it all behavioural and unsynthesisable?
- Altera_Forum
Let me clarify. The Verilog (sorry i said VHDL by mistake earlier) code that I have is working correctly i.e. if I specify the bmp file as input it produces (encodes) a jpeg file.
I need processors which will run each module of my set of Verilog. eg. I have a DCT (Discrete cosine transform) module but need the processor elements to run this module. The idea is to design each processor separately to run each element and then create a "Network On Chip" communication system to run all the encoding models. Thanks for your suggestion ! - Altera_Forum
What do you mean by processor blocks?
Is your VHDL/Verilog synthesisable or not? Some or all of it? - Altera_Forum
I have not checked whether it is synthesizable or not yet. In fact, I am not aware that there is a synthesis step ! I guess, the next step would be check and then make the code synthesizable ....
- Altera_Forum
Hello
I am doing same project. But i am not knowing verilog much more. Right now i m working on verilog. Please tell me how to start my project means give me steps to starting the project as well as give me some brief idea on JPEG encoder and how to implement it with verilog.
