Hi everybody, we just started with a new project which will use an Cyclone III. We ant to reuse as much of our previous code which was done for Xilinx FPGA. Most file are quite genric, but some contain components from xilinx library. We would replace this part with using if generate constructs, depending on FPGA types, but there is still the unisim library declaration at the top of the file. As anybody had any expirience with that ? i thought about making a dummy unisim library which conatins the used components, to be able to actually compile the code. Is that the right approach ?

VHDL libraries are added via the tool(i.e. the VHDL says the name of the library but the Quartus .qsf or ISE file specifies what file to read in that has the library.) One idea might be to make an empty UNISIM library and add that to the Quartus project. Since nothing is neeeded out of it, it should work out all right. (I haven't tried it, but think it would work.)

It may be useful to add wrappers to Altera MegaFunctions for some UNISIM components, e.g. RAM-blocks, if they are frequently used in your design. See http://www.alteraforum.com/forum/showthread.php?t=1167

Hi I've just started pretty well the same process as well. I am interested in knowing is there a datasheet for all the Altera "design elements" (ie Xilinx has DCM's, BRAMS etc etc) I have looked at the MegaWizard which seems to contain these sorts of things, but no datasheets seem to be avail... Also is there an equivalent to the unisim library? With Xilinx you would just do: library unisim; use unisim.vcomponents.all; and would be able to instantiate any of the Xilinx design elements. I have found the altera_mf and seem to have successfully instantiated the alt_shift_taps into my design library altera_mf; use work.altera_mf_components.all; but I'm not confident that this is how Altera intended. Do you have to go through the MegaWizard and create all the components by hand? And if so then what happens when the next version of Quartus comes out and subtle changes are made to the design elements?? Do you have to do them all again?? Thanks

I would suggest using the MegaWizard, and using the recommended flow of just instantiating the created file(I've seen people use the Megawizard to create something like a PLL, then rip the primitive instantiation out of the megafunction and put it into their file. This is ugly because it creates something that can't be re-edited/analyzed/updated with the megawizard, and usually has a bunch of parameters the user starts mucking with yet doesn't understand them). My experience is that a lot of Xilinx designers use the low-level primitives and Altera designers use the high-level megafunctions(which in many cases, like a PLL or altsyncram, aren't that high-level). You could probably get a good message board of people going back and forth on it. I don't like the Xilinx methodology because you often end up spending too much time figuring out low-level parameters or ports to do a high-level function, and the final instantiation doesn't make any sense to a casual observer(where a megafunction can be re-opened and is usually pretty clear.) That being said, there are times when you want to know the low-level details and have trouble figuring it out in the megafunction. The Xilinx DSP blocks are a good case, where I've seen people basically put in op-codes to do something like a multiply-add. There was no way to figure out what it was doing without going to the datasheet and finding this op-code, so for the general case it was painful. But for someone who is changing those op-codes on the fly and doing some funky stuff with it, it was pretty cool. You'll also find Altera's low-leve primitive documentation isn't the best, while their megafunctions are usually quite good(and Xilinx tends to be the opposite, although I haven't looked in a while, and there are always cases that these aren't true). Altera's documentation is more the device handbook, which describes the PLL, the DSP block, the memory blocks, etc., and then the megafunctions are used to access those blocks. Anyway, that's just my feeling, but hope it helps. (Not sure if I really answered your question rather than wax philosophical...)

Hi Rysc Thanks for your response. I found the user guides section on the web, which is what I was looking for - has info on mem, pll etc so possibly my documentation needs have been forfilled. I created a PLL through the megawizard and was happy to find that the resulting VHD file was referencing the altera_mf in the same way that I did it manually. The problem that I currently face in using the megawizard is that I have to use it each time I want to ie: create a PLL with a different mult/div ratio, as I cant bring those generics out of the wrapper entity. I would rather have one PLL file that has some flexiblilty rather than multiple 'dedicated' PLL's. I think I really only need to convert the DCM's and the BRAMs across as the rest is just VHDL. I'll probably use the megawizard output as a reference and then make my custom file, bringing out the generics that I want to keep flexible, plus maybe add a few comments to attempt to keep the confusion to a minimum :)

Porting from Xilinx to Altera | Altera Community

13 Replies

Altera_Forum
Honored Contributor
17 years ago
I made dummy libraries from Xilinx and Altera stuff (unisim, altera_mf) containing the components declaration. If we can now compile our design on both plattform, during synthesis if just load the dummy xlinx lib in quartus, and it won't complain that it can't find unisim lib.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
I made dummy libraries from Xilinx and Altera stuff (unisim, altera_mf) containing the components declaration. If we can now compile our design on both plattform, during synthesis if just load the dummy xlinx lib in quartus, and it won't complain that it can't find unisim lib.
--- Quote End ---

Would You ( or somene else ) please share dummy library from Xilinx (unisim )?

What if I will just comment out that line "use UNISIM.VComponents.all;" ?
After commenting out that line everywhere it appeared Quartus compiled the project OK.
Does this simple "use UNISIM.VComponents.all;" removal makes the same effect as using dummy library?
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Would You ( or somene else ) please share dummy library from Xilinx (unisim )?

What if I will just comment out that line "use UNISIM.VComponents.all;" ?
After commenting out that line everywhere it appeared Quartus compiled the project OK.
Does this simple "use UNISIM.VComponents.all;" removal makes the same effect as using dummy library?
--- Quote End ---

No, I can't. Just take the unisim file from xilinx (it's called unisim.vhd or so), copy it somewhere, and remove all non component declaration. It took me an hour to so to do.

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Porting from Xilinx to Altera

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