porting code from SRAM to SSRAM, bursting confusion

Hi all,

I'm trying to port some code which used an SRAM chip on a DE1 board, to use the SSRAM chip on a DE2-70 board.

My main concern and confusion is the fact that SSRAM uses bursting.

The code which used the DE1 SRAM, supplied "random" addresses constantly to the controller every clock cycle, and expected valid data after a 3 clock cycle delay (input and output ports were registered), effectively pipelining the read transfers with just 1 clock delay.

Now, my question: Is it possible to supply "random" addresses every clock cycle aswell to the SSRAM controller, without using the bursting feature, ie. always do a single read, and expect data with a 3 clock cycle pipeline delay?

Reading some information about the workings of an SSRAM seem to suggest that a single read must be completed first, before new addresses can be supplied. This is why bursting was invented - this would be very bad, as this would not allow pipelining of random address reads.

Can anyone shed some light on this? Thanks.