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Honored Contributor
Honored Contributorporting code from SRAM to SSRAM, bursting confusion
Hi all, I'm trying to port some code which used an SRAM chip on a DE1 board, to use the SSRAM chip on a DE2-70 board. My main concern and confusion is the fact that SSRAM uses bursting. ...
Altera_ForumHonored Contributor
Honored ContributorRead from arbitary addresses can be performed with SSRAM @CLK/2 throughput while burst read achieves full CLK speed. So you have to use a double clock speed for the SSRAM related to your data clock. This shouldn't be an issue, considering it's timing specification. The design complexity increases, however.
