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Altera_Forum
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14 years ago

Port Assignment Problem

I have two boards of Cyclone III EP3C120F780C7N, say board A and board B. I have developed USB device and ported to FPGA: I have two issues while mapping the assignments 1) The USB devic...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

It could be a timing problem. Are your I/O properly constrained, and does the design meet timing requirements?

A design that works on some boards and not on others usually means there is a timing violation somewhere (if you can exclude for sure a hardware failure on the bad boards).