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Altera_Forum's avatar
Altera_Forum
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14 years ago

Port Assignment Problem

I have two boards of Cyclone III EP3C120F780C7N, say board A and board B.

I have developed USB device and ported to FPGA:

I have two issues while mapping the assignments

1) The USB device is working on port B of board A, also I have properly mapped the ports to port A on the same board, the USB is not working.

2) I am using same SOF file on both the boards, the USB works on A board and doesnot work on the B board.

Can I know, if anyone have come across the same issue before and how to validate the board.

Thanks and Regards,

Vijay K

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You'll have to be more specific. What components did you use for the USB interface, and what does 'not working' mean?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Sorry for the late reply,

    we have the customised USB IP on FPGA.

    If I use Port x, I am able to identify the USB device using libusb -vvv

    and

    not working means, if I use the same SOF file on port x different board of same kind. I am not able to enumerate or identify the USB device.

    Can I know what might be the reason for this.

    Thanks ,

    Vijay K
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    It could be a timing problem. Are your I/O properly constrained, and does the design meet timing requirements?

    A design that works on some boards and not on others usually means there is a timing violation somewhere (if you can exclude for sure a hardware failure on the bad boards).