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Altera_Forum's avatar
Altera_Forum
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14 years ago

PLLx_OUTp && PLLx_OUTn

Hello,

In the Spec. of Cyclone handbook, the PLL1_OUTp and PLL1_OUTn ard described as : Single-ended or LVDS pins driven by the e0 port from PLL1.

How to configure the two pins if I want to get a pair of differential clock ? 1. Set the I/O standard as LVDS ?

2. drive the PLL1_OUTp by e0 of PLL1 ?

3. and ... ?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    That's it. The PLL1_OUTn will be assigned and driven based on the LVDS IO standard.

    Pete