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Altera_Forum's avatar
Altera_Forum
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8 years ago

PLL's in Cyclone V

Hello,

I am trying to use the output of a PLL to drive a logic in FPGA. I'm not sure which clock should be connected as the 'refclk' for the PLL and how the 'outclk' of the PLL should clock my logic.

I have tried using a 50MHz clock (PIN AF_14) as a refclk for the PLL, and used the PLL 'outclk' as a clock input but my logic does produce any output. Could you please help?

Also, when I check my logic in ModelSim, the correct results are obtained.

Thank you.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hello,

    Apologies for the late reply. I did a lot of trial and error tests. I was able to achieve higher clock speeds. But I wanted to confirm if this is the right way. Here is the top level code:

    module top(

    input clk,

    input rst,

    input driver_clk,

    output pll_out,

    output locked_port,

    output data

    );

    driver d1(

    .clk(driver_clk),

    .rst(rst),

    .data_out(data)

    );

    pll pll_inst (

    .refclk (clk), // refclk.clk

    .rst (rst), // reset.reset

    .outclk_0 (pll_out), // outclk0.clk

    .locked (locked_port) // locked.export

    );

    endmodule

    The pll_out port is connected to PIN_AH12 and I am using driver_clk is connected to PIN_AJ12 which is the the clock input for the driver module. The 'data' port is connected to HSMC pin 'PIN_B13' and I have also assigned the 'pll_outclk' as a GCLK.

    Is this the right way to go about? Because my output signal have a lot of jitters and distortions.

    Thanks for all your help.