PLL's in Cyclone V

Hello,

Apologies for the late reply. I did a lot of trial and error tests. I was able to achieve higher clock speeds. But I wanted to confirm if this is the right way. Here is the top level code:

module top(

input clk,

input rst,

input driver_clk,

output pll_out,

output locked_port,

output data

);

driver d1(

.clk(driver_clk),

.rst(rst),

.data_out(data)

);

pll pll_inst (

.refclk (clk), // refclk.clk

.rst (rst), // reset.reset

.outclk_0 (pll_out), // outclk0.clk

.locked (locked_port) // locked.export

);

endmodule

The pll_out port is connected to PIN_AH12 and I am using driver_clk is connected to PIN_AJ12 which is the the clock input for the driver module. The 'data' port is connected to HSMC pin 'PIN_B13' and I have also assigned the 'pll_outclk' as a GCLK.

Is this the right way to go about? Because my output signal have a lot of jitters and distortions.

Thanks for all your help.